keep-out area A region of a circuit board where specific items such as components, conductors and holes cannot be placed during layout. The restriction may be as a result of electrical constraints (such as clearance for high voltage), mechanical constraints (such as requirement to fit boards close to each other), or process reasons (where clearance is needed for the correct operation of assembly equipment).

keying A mechanical method of preventing incorrect interconnection of mating components (such as connectors).

KGD = Known Good Die Most semiconductor die are tested at wafer stage, using probes. Unfortunately, these tests are rarely at full operating frequency, or cover the whole range of possible fault modes. As a result, when probe-tested chips are assembled into a package, there is usually some drop-out. The problem with multi-chip modules and other COB applications is that failures create at best a re-work ‘opportunity’, and at worst a complete failure of the entire module. There is therefore pressure on suppliers to test chips more fully, and this is done by a variety of methods, most of which involve making a quasi-permanent contact to the chip surface.

Known Good Board See gold board.